Communication between electronic devices is drawing more attention as the speeds of such electronic devices increase. One type of electronic communications architecture for interconnecting electronic devices is the RAPIDIO standard, described in “The RapidIO™ Interconnect Specification,” Revision 1.2, June, 2002, published by the RapidIO Trade Association. The RAPIDIO architecture is configured for interconnecting microprocessors, digital signal processors (DSPs), communications and network processors, system memory, peripheral devices, and the like on a circuit board or several circuit boards using a backplane. The RAPIDIO architecture provides for packet-switched point-to-point technology for passing data and control information within embedded systems, primarily used in network and communications equipment.
In a RAPIDIO system, two ports are interconnected via a link. Each port has a transmitter and a receiver connected to the other port's receiver and transmitter, respectively. In the serial mode, a full duplex serial interface between endpoint devices is provided using unidirectional differential signals in each direction. A RAPIDIO system may be implemented within an integrated circuit, such as a programmable logic device.
Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBS) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
In the RAPIDIO standard, an endpoint device must perform a recovery process if a given transmitted packet has not been acknowledged after approximately three seconds (“expiration period”). In the serial mode, an endpoint device can have up to 32 outstanding packets at any given moment. If a given packet has been unacknowledged past the expiration period, the packet has expired and the recovery process is triggered. In the recovery process, the endpoint device resends the expired packet and all packets that have been sent after the expired packet. As the recovery process begins, all timers for outstanding packets are cleared, even if they have not expired (i.e., an expiration of one packet is treated as an expiration of all unacknowledged packets).
Conventionally, an endpoint device configured for serial RAPIDIO communication employs 32 large counters (i.e., a counter for each possible outstanding packet). If the endpoint device is implemented with an FPGA, such an architecture consumes a significant amount of programmable resources. Specifically, for an FPGA running at 156.25 MHz, the counters require 29 bits (i.e., 229 cycles/156,250,000 cycles/sec is approximately equal to 3.4 seconds). A register implementation of the counters would require 928 registers (i.e., 29 times 32) and 32 carry chains.
Accordingly, there exists a need in the art for a method and apparatus that detects timeout for packets transmitted in a packet-switched point-to-point communication architecture employing minimal logic resources.